Conceptualize a Design Flow for 2-D Bitstream Relocation

Date

Apr 17, 2018

Time

1:00 PM - 2:00 PM

Speaker

Najdet Charaf

Affiliation

Institut für Technische Informatik, Professur Prozessordesign

Language

en

Main Topic

Informatik

Other Topics

Informatik

Description

Runtime partial reconfiguration provides a high flexibility and time share capabilities on FPGAs. However, designs with several reconfigurable partitions (RPs) and several reconfigurable modules (RMs) generate a lot of partial bitstreams (PBs) for all possible RP/RM pairs. In addition, the time needed to generate all PBs increases with the number of RPs and RMs. For this purpose, bitstream relocation is an approach that provides a less storage usage and reduces the time needed for generating all possible PBs. This diploma thesis presents an automated floorplanning approach and a fully automated design flow for 1-D and 2-D bitstream relocation. The algorithm was implemented for Xilinx Vivado Design Suite and works on any Xilinx Series 7 devices. Diese Veranstaltung wird unterstützt von Professur Prozessordesign.

Last modified: Apr 17, 2018, 9:49:12 AM