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UID:DSC-14314
DTSTART;TZID=Europe/Berlin:20180417T130000
SEQUENCE:1523951352
TRANSP:OPAQUE
DTEND;TZID=Europe/Berlin:20180417T140000
URL:https://www.dresden-science-calendar.de/calendar/en/detail/14314
LOCATION:TUD Georg-Schumann-Bau\, Münchner Platz 301187 Dresden
SUMMARY:Charaf: Conceptualize a Design Flow for 2-D Bitstream Relocation
CLASS:PUBLIC
DESCRIPTION:Speaker: Najdet Charaf\nInstitute of Speaker: Institut für Tec
 hnische Informatik\, Professur Prozessordesign\nTopics:\nInformatik\n Loca
 tion:\n  Name: TUD Georg-Schumann-Bau (Georg-Schumann-Str. 7A\, 2. OG Raum
  204)\n  Street: Münchner Platz 3\n  City: 01187 Dresden\n  Phone: \n  Fa
 x: \nDescription: Runtime partial reconfiguration provides a high flexibil
 ity and time share capabilities on FPGAs. However\, designs with several r
 econfigurable partitions (RPs) and several reconfigurable modules (RMs) ge
 nerate a lot of partial bitstreams (PBs) for all possible RP/RM pairs. In 
 addition\, the time needed to generate all PBs increases with the number o
 f RPs and RMs. For this purpose\, bitstream relocation is an approach that
  provides a less storage usage and reduces the time needed for generating 
 all possible PBs. This diploma thesis presents an automated floorplanning 
 approach and a fully automated design flow for 1-D and 2-D bitstream reloc
 ation. The algorithm was implemented for Xilinx Vivado Design Suite and wo
 rks on any Xilinx Series 7 devices. Diese Veranstaltung wird unterstützt 
 von <b>Professur Prozessordesign</b>.
DTSTAMP:20260419T001024Z
CREATED:20180414T074530Z
LAST-MODIFIED:20180417T074912Z
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