Model Checking Architectural Descriptions: Software and Hardware

Date

Apr 9, 2015

Time

3:00 PM - 4:00 PM

Speaker

Chadlia Jerad

Affiliation

École Nationale des Sciences de l’Informatique und École Nationale d'Ingénieurs de Tunis, Tunesien

Series

TUD ZIH Kolloquium

Language

en

Main Topic

Informatik

Other Topics

Informatik

Host

Ralph Müller-Pfefferkorn, Zentrum für Informationsdienste und Hochleistungsrechnen

Description

Increasing complexity in software as well as in hardware systems, leads to the need of techniques to formally check design properties. This is especially important for safety critical systems. Architectural descriptions allow designers to focus on high level aspects of a system by leaving aside details or on better terms by abstracting these details. It is precisely this abstraction that makes these models suitable for formal verification using model checking techniques. The presentation will overview architecture description languages (mainly software, but also hardware), as well as model checking techniques. A particular focus will be made on the use of Maude, an executable specification language based on rewriting logic, and its LTL model checker for describing and verifying properties.
Chadlia Jerad received the Electrical Engineering degree and the Master degree from the National Engineering School of Tunis (ENIT), Tunisia. For her Ph.D., she worked on rewriting logic based formal verification of software architecture description languages. Since 2009, she joined the National School of Computer Science, Tunisia as an associate Professor. Now she is the coordinator of “Embedded Systems and Software Specialization”. She joined OASIS Laboratory at ENIT starting 2012. Her research interests include formal verification, architecture description (software and hardware), and MPSoC.

Links

• http://tu-dresden.de/veranstaltungen/termin?id=TUD5523eebfe37c8

Last modified: Apr 9, 2015, 9:40:09 AM