Graph Algorithms on Emerging Tile-Centric Accelerators
- Date
- Aug 22, 2024
- Time
- 3:00 PM - 4:30 PM
- Speaker
- Johannes Langguth
- Affiliation
- University of Bergen, Norway
- Language
- en
- Main Topic
- Informatik
- Other Topics
- Informatik
- Description
A major recent development in computer hardware was the rise of dedicated accelerator hardware for machine learning applications such as the Graphcore IPUs and Cerebras WSE. These processors have evolved from the experimental state into market-ready products, and they have the potential to constitute the next major architectural shift after GPUs saw widespread adoption a decade ago.
A salient feature of these devices is the use of SRAM for memory, which offers very low latency and high bandwidth, making them attractive for a wide range of graph algorithms. On the other hand, the wide parallelism employed in these devices makes it difficult to use them efficiently for irregular computations.
In this talk we will present the new hardware and discuss the programming techniques that are required to unlock their potential. We present implementations of basic graph algorithms and show early results on the attainable performance, as well as comparisons to other architectures. We follow up by discussing the wider implications of the architecture for algorithm design and programming.
Johannes Langguth is a Senior Research Scientist at Simula Research Laboratory, and an Associate Professor at the University of Bergen, Norway.
Prior to that, he worked at ENS Lyon, France. His research is centred around architectures, algorithms, and applications of parallel graph algorithms and sparse linear algebra. His previous projects include interdisciplinary work on social network analysis using combinations of network science, GNNs, and NLP, as well as parallel matching algorithms for combinatorial scientific computing and performance optimization for irregular applications the European High-Performance Computing project SparCity. Recent work has focussed on graph algorithms on tile-centric accelerators such as Graphcore IPUs and Cerebras WSEs, providing the first implementations of several algorithms on these platforms.
ONLINE: Link ZIH-Colloquia (https://bbb.tu-dresden.de/b/har-oa6-col-lmy)
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Last modified: Aug 22, 2024, 7:38:37 AM
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